1. Field of Disclosure
The present disclosure relates generally to testing of a memory and specifically to measuring a read speed of the memory.
2. Related Art
A memory is an electronic device for reading and/or writing electronic data. Each bit of the electronic data can be read from and/or written into a memory cell. Each of the memory cells can be coupled to one another to form an array of memory cells, or simply a memory, which can be accessible through various control lines that can be selected or toggled to read and/or write the electronic data. The memory can be implemented as volatile memory, such as random access memory (RAM), which requires power to maintain its stored information or non-volatile memory, such as read-only memory (ROM), which can maintain its stored information even when not powered. The RAM can be implemented in a dynamic random-access memory (DRAM), a static random-access memory (SRAM), and/or a non-volatile random-access memory (NVRAM), often referred to as a flash memory, configuration.
The two basic operations performed by the memory are “read”, in which the electronic data stored in memory cells that correspond to a memory word is read out, and “write” in which the electronic data is stored in memory cells that correspond to a memory word. During an asynchronous read operation, a memory controller asserts an n bit address of memory cells on address control lines while driving a chip enable control line (CE#) and an output enable control line (OE#). The n bit address is latched by the memory at a falling edge of the CE#. One or more row decoders decode a first portion of the n bit address to read a word of data from memory cells that correspond to the first portion of the n bit address. A column decoder decodes a second portion of the n bit address to access a block of bits from among the word that corresponds to the second portion of the n bit address. During a page read operation, one or more bits the second portion of the n bit address can be sequenced to read multiple words, referred to as a page, of the electronic data.
One benchmark for memory performance is the read speed access time or simply read speed. Design for Test (DFT), also referred to as “Design for Testability”, in a context of a memory, supplements a design of a memory with testability features to provide improved access to internal circuit elements of the memory to more easily control and/or observe these internal circuit elements to measure the read speed of the memory.
The present disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.